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High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip
by Zheng Wang and Anupam Chattopadhyay
Overview
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
This item is Non-Returnable
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Details
- ISBN-13: 9789811093210
- ISBN-10: 9811093210
- Publisher: Springer
- Publish Date: May 2018
- Dimensions: 9.21 x 6.14 x 0.46 inches
- Shipping Weight: 0.69 pounds
- Page Count: 197
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