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{
"item_title" : "Advanced ASIC Chip Synthesis",
"item_author" : [" Himanshu Bhatnagar "],
"item_description" : "Foreword. Preface. Acknowledgements. About the Author. 1. ASIC Design Methodology. 2. Tutorial. 3. Basic Concepts. 4. Synopsys Technology Library. 5. Partitioning and Coding Styles. 6. Constraining Designs. 7. Optimizing Designs. 8. Design for Test. 9. Links to Layout & Post-Layout Optimization. 10. SDF Generation. 11. PrimeTime Basics. 12. Static Timing Analysis. Appendix. Index.",
"item_img_path" : "https://covers3.booksamillion.com/covers/bam/0/79/238/537/0792385373_b.jpg",
"price_data" : {
"retail_price" : "99.00", "online_price" : "99.00", "our_price" : "99.00", "club_price" : "99.00", "savings_pct" : "0", "savings_amt" : "0.00", "club_savings_pct" : "0", "club_savings_amt" : "0.00", "discount_pct" : "10", "store_price" : ""
}
}
Advanced ASIC Chip Synthesis : Using Synopsysa (R) Design Compilera (R) and Primetimea (R)
Overview
Foreword. Preface. Acknowledgements. About the Author. 1. ASIC Design Methodology. 2. Tutorial. 3. Basic Concepts. 4. Synopsys Technology Library. 5. Partitioning and Coding Styles. 6. Constraining Designs. 7. Optimizing Designs. 8. Design for Test. 9. Links to Layout & Post-Layout Optimization. 10. SDF Generation. 11. PrimeTime Basics. 12. Static Timing Analysis. Appendix. Index.
This item is Non-Returnable
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Details
- ISBN-13: 9780792385370
- ISBN-10: 0792385373
- Publisher: Kluwer Academic Publishers
- Publish Date: May 1999
- Dimensions: 9.21 x 6.14 x 0.75 inches
- Shipping Weight: 1.36 pounds
- Page Count: 316
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