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On-Chip Training Npu - Algorithm, Architecture and Soc Design|Donghyeon Han

On-Chip Training Npu - Algorithm, Architecture and Soc Design

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Overview

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.

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Details

  • ISBN-13: 9783031342363
  • ISBN-10: 3031342364
  • Publisher: Springer
  • Publish Date: July 2023
  • Dimensions: 9.21 x 6.14 x 0.63 inches
  • Shipping Weight: 1.19 pounds
  • Page Count: 237

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