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{ "item_title" : "Hardware Architectures for Post-Quantum Digital Signature Schemes", "item_author" : [" Deepraj Soni", "Kanad Basu", "Mohammed Nabeel "], "item_description" : "This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;Enables designers to build hardware implementations that are resilient to a variety of side-channels.", "item_img_path" : "https://covers2.booksamillion.com/covers/bam/3/03/057/681/3030576817_b.jpg", "price_data" : { "retail_price" : "119.99", "online_price" : "119.99", "our_price" : "119.99", "club_price" : "119.99", "savings_pct" : "0", "savings_amt" : "0.00", "club_savings_pct" : "0", "club_savings_amt" : "0.00", "discount_pct" : "10", "store_price" : "" } }
Hardware Architectures for Post-Quantum Digital Signature Schemes|Deepraj Soni

Hardware Architectures for Post-Quantum Digital Signature Schemes

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Overview

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.

  • Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
  • Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
  • Enables designers to build hardware implementations that are resilient to a variety of side-channels.

This item is Non-Returnable

Details

  • ISBN-13: 9783030576813
  • ISBN-10: 3030576817
  • Publisher: Springer
  • Publish Date: October 2020
  • Dimensions: 9.21 x 6.14 x 0.5 inches
  • Shipping Weight: 0.99 pounds
  • Page Count: 170

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