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"item_title" : "Next-Generation Floating-Point Arithmetic Unit",
"item_author" : [" A. Arunkumar Gudivada", "Emandi Jagadeeswara Rao "],
"item_description" : "The Next-Generation Floating-Point Arithmetic Unit Using QCA for Low-Power Applications explores the use of Quantum-dot Cellular Automata for implementing a Floating-Point Arithmetic Unit at the Nano-scale, overcoming limitations of CMOS technology. The research involves designing efficient QCA-based 1-bit and 8-bit full adders, multipliers, and a novel Tree-Based Stack-Type comparator. The proposed FPAU is tested through the implementation of a Fast Fourier Transform algorithm, demonstrating significant improvements in area, power dissipation, and delay compared to existing CMOS-based architectures.",
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Next-Generation Floating-Point Arithmetic Unit
Overview
The Next-Generation Floating-Point Arithmetic Unit Using QCA for Low-Power Applications explores the use of Quantum-dot Cellular Automata for implementing a Floating-Point Arithmetic Unit at the Nano-scale, overcoming limitations of CMOS technology. The research involves designing efficient QCA-based 1-bit and 8-bit full adders, multipliers, and a novel Tree-Based Stack-Type comparator. The proposed FPAU is tested through the implementation of a Fast Fourier Transform algorithm, demonstrating significant improvements in area, power dissipation, and delay compared to existing CMOS-based architectures.
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Details
- ISBN-13: 9786208117252
- ISBN-10: 6208117259
- Publisher: LAP Lambert Academic Publishing
- Publish Date: September 2024
- Dimensions: 9 x 6 x 0.34 inches
- Shipping Weight: 0.49 pounds
- Page Count: 144
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