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{ "item_title" : "Physical Design Essentials", "item_author" : [" Khosrow Golshan "], "item_description" : "Physical Design Essentials is arranged in a format that follows the industry-common ASIC physical design flow. Its target audience is today's physical design engineers or professionals in the ASIC area that are expected to be conversant with all aspects of ASIC design implementation stages including device processes, library development, place-and-route algorithms, verification and testing. It begins with general concepts of an ASIC library, then covers floor planning, placement, routing, verification, and finally, testing.Topics covered include: Basic standard cell design, transistor-sizing, and layout styles; Linear, non-linear, and polynomial characterization; Physical design constraints and floor planning styles; Algorithms used for placement Clock Tree Synthesis; Algorithms used for global and detailed routing; parasitic extraction; Functional timing and physical methods of verification; Electronic Testing.", "item_img_path" : "https://covers2.booksamillion.com/covers/bam/0/38/736/642/0387366423_b.jpg", "price_data" : { "retail_price" : "169.99", "online_price" : "169.99", "our_price" : "169.99", "club_price" : "169.99", "savings_pct" : "0", "savings_amt" : "0.00", "club_savings_pct" : "0", "club_savings_amt" : "0.00", "discount_pct" : "10", "store_price" : "" } }
Physical Design Essentials|Khosrow Golshan

Physical Design Essentials : An ASIC Design Implementation Perspective

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Overview

Physical Design Essentials is arranged in a format that follows the industry-common ASIC physical design flow. Its target audience is today's physical design engineers or professionals in the ASIC area that are expected to be conversant with all aspects of ASIC design implementation stages including device processes, library development, place-and-route algorithms, verification and testing. It begins with general concepts of an ASIC library, then covers floor planning, placement, routing, verification, and finally, testing.

Topics covered include: Basic standard cell design, transistor-sizing, and layout styles; Linear, non-linear, and polynomial characterization; Physical design constraints and floor planning styles; Algorithms used for placement Clock Tree Synthesis; Algorithms used for global and detailed routing; parasitic extraction; Functional timing and physical methods of verification; Electronic Testing.

This item is Non-Returnable

Details

  • ISBN-13: 9780387366425
  • ISBN-10: 0387366423
  • Publisher: Springer
  • Publish Date: May 2007
  • Dimensions: 9.21 x 6.14 x 0.56 inches
  • Shipping Weight: 1.11 pounds
  • Page Count: 212

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