{ "item_title" : "A Pipelined Multi-Core Machine with Operating System Support", "item_author" : [" Petro Lutsyk", "Jonas Oberhauser", "Wolfgang J. Paul "], "item_description" : "This work is building on results from the book named A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness by M. Kovalev, S.M. M ller, and W.J. Paul, published as LNCS 9000 in 2014.It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:- MIPS instruction set architecture (ISA) for application and for system programming- cache coherent memory system- store buffers in front of the data caches- interrupts and exceptions- memory management units (MMUs)- pipelined processors: the classical five-stage pipeline is extended by two pipelinestages for address translation- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)- I/O-interrupt controller and a disk", "item_img_path" : "https://covers4.booksamillion.com/covers/bam/3/03/043/242/3030432424_b.jpg", "price_data" : { "retail_price" : "54.99", "online_price" : "54.99", "our_price" : "54.99", "club_price" : "54.99", "savings_pct" : "0", "savings_amt" : "0.00", "club_savings_pct" : "0", "club_savings_amt" : "0.00", "discount_pct" : "10", "store_price" : "" } }

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