Timing Optimization Through Clock Skew Scheduling
Overview
The focus of this book is on timing analysis and optimization techniques for circuits with level-sensitive memory elements (registers). Level-sensitive registers are becoming significantly more popular in practice as integrated circuit densities are increasing and the 'performance-per-power' metric for integrated circuits becomes a key issue. Therefore, techniques for understanding level-sensitive based circuits and for optimizing the performance of such circuits are increasingly important. The book contains a linear programming formulation applicable to the timing analysis of large scale circuits. It includes a delay insertion methodology, and offers an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology.
This item is Non-Returnable
Customers Also Bought
Details
- ISBN-13: 9780387710556
- ISBN-10: 0387710558
- Publisher: Springer
- Publish Date: November 2008
- Dimensions: 9.21 x 6.14 x 0.69 inches
- Shipping Weight: 1.27 pounds
- Page Count: 266
Related Categories
