Transactions on High-Performance Embedded Architectures and Compilers II
Overview
Special Section on High-Performance Embedded Architectures and Compilers.- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.- Compiler-Assisted Memory Encryption for Embedded Processors.- Branch Predictor Warmup for Sampled Simulation through Branch History Matching.- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.- Regular Papers.- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.- Fetch Gating Control through Speculative Instruction Window Weighting.- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.- Linux Kernel Compaction through Cold Code Swapping.- Complexity Effective Bypass Networks.- A Context-Parameterized Model for Static Analysis of Execution Times.- Reexecution and Selective Reuse in Checkpoint Processors.- Compiler Support for Code Size Reduction Using a Queue-Based Processor.- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.
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Details
- ISBN-13: 9783642009037
- ISBN-10: 3642009034
- Publisher: Springer
- Publish Date: April 2009
- Dimensions: 9.37 x 6.3 x 0.78 inches
- Shipping Weight: 1.15 pounds
- Page Count: 327
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