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{ "item_title" : "Verification Techniques for System-Level Design", "item_author" : [" Masahiro Fujita", "Indradeep Ghosh", "Mukul Prasad "], "item_description" : "This book will explain how to verify SoC (Systems on Chip) logic designs using formal and semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.", "item_img_path" : "https://covers1.booksamillion.com/covers/bam/0/12/370/616/0123706165_b.jpg", "price_data" : { "retail_price" : "101.00", "online_price" : "101.00", "our_price" : "101.00", "club_price" : "101.00", "savings_pct" : "0", "savings_amt" : "0.00", "club_savings_pct" : "0", "club_savings_amt" : "0.00", "discount_pct" : "10", "store_price" : "" } }
Verification Techniques for System-Level Design|Masahiro Fujita

Verification Techniques for System-Level Design

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Overview

This book will explain how to verify SoC (Systems on Chip) logic designs using "formal" and "semiformal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.

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Details

  • ISBN-13: 9780123706164
  • ISBN-10: 0123706165
  • Publisher: Morgan Kaufmann Publishers
  • Publish Date: November 2007
  • Dimensions: 9.24 x 7.64 x 0.86 inches
  • Shipping Weight: 1.47 pounds
  • Page Count: 256

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