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{ "item_title" : "Behavioral Synthesis for Hardware Security", "item_author" : [" Srinivas Katkoori", "Sheikh Ariful Islam "], "item_description" : "Introduction.- Background.- Techniques for algorithm-level obfuscation during high-level synthesis.- High-level synthesis of key based obfuscated RTL datapaths.- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation.- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.- Behavioral synthesis techniques for intellectual property protection.- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.- High-Level Synthesis for Side-Channel Defense.- On state encoding against power analysis attacks for finite state controllers.- Examining the consequences of high-level synthesis optimizations on power side-channel.- Towards a timing attack aware high-level synthesis of integrated circuits.- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement.- Mitigating information leakage during critical communication using S*FSM.- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security-Driven Task Scheduling.- Securing industrial control system with high level synthesis.- Conclusions and open research problems.", "item_img_path" : "https://covers4.booksamillion.com/covers/bam/3/03/078/840/3030788407_b.jpg", "price_data" : { "retail_price" : "139.99", "online_price" : "139.99", "our_price" : "139.99", "club_price" : "139.99", "savings_pct" : "0", "savings_amt" : "0.00", "club_savings_pct" : "0", "club_savings_amt" : "0.00", "discount_pct" : "10", "store_price" : "" } }
Behavioral Synthesis for Hardware Security|Srinivas Katkoori

Behavioral Synthesis for Hardware Security

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Overview

Introduction.- Background.- Techniques for algorithm-level obfuscation during high-level synthesis.- High-level synthesis of key based obfuscated RTL datapaths.- RTL Hardware IP protection Using Key-Based Control and Data Flow Obfuscation.- Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.- Behavioral synthesis techniques for intellectual property protection.- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.- High-Level Synthesis for Side-Channel Defense.- On state encoding against power analysis attacks for finite state controllers.- Examining the consequences of high-level synthesis optimizations on power side-channel.- Towards a timing attack aware high-level synthesis of integrated circuits.- High-Level Synthesis with Timing-Sensitive Information Flow Enforcement.- Mitigating information leakage during critical communication using S*FSM.- Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security-Driven Task Scheduling.- Securing industrial control system with high level synthesis.- Conclusions and open research problems.

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Details

  • ISBN-13: 9783030788407
  • ISBN-10: 3030788407
  • Publisher: Springer
  • Publish Date: February 2022
  • Dimensions: 9.21 x 6.14 x 0.94 inches
  • Shipping Weight: 1.67 pounds
  • Page Count: 398

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