{ "item_title" : "Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS", "item_author" : [" Brandon Noia", "Krishnendu Chakrabarty "], "item_description" : "This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. ", "item_img_path" : "https://covers4.booksamillion.com/covers/bam/3/31/902/377/3319023772_b.jpg", "price_data" : { "retail_price" : "109.99", "online_price" : "109.99", "our_price" : "109.99", "club_price" : "109.99", "savings_pct" : "0", "savings_amt" : "0.00", "club_savings_pct" : "0", "club_savings_amt" : "0.00", "discount_pct" : "10", "store_price" : "" } }

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