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{
"item_title" : "Digital System Test and Testable Design",
"item_author" : [" Zainalabedin Navabi "],
"item_description" : "Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods",
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Digital System Test and Testable Design : Using Hdl Models and Architectures
Overview
Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods
This item is Non-Returnable
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Details
- ISBN-13: 9781441975478
- ISBN-10: 1441975470
- Publisher: Springer
- Publish Date: December 2010
- Dimensions: 10 x 7 x 1 inches
- Shipping Weight: 2.22 pounds
- Page Count: 435
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